Methods and apparatuses consistent with exemplary embodiments relate to tracking activations to rows of memory, and more particularly to a method and apparatus for efficiently tracking activations to rows of memory using a reduced number of row activation counters.
When a target row of a dynamic random access memory (DRAM) is activated too many times within a time period, the data stored at adjacent rows, which are physically adjacent to the target row, may be disturbed or lost. In particular, due to increasing density of DRAM design, the data stored at an adjacent row may be corrupted due to noise generated from the frequent activation of the target row.
Accordingly, for some DRAM devices, a manufacturer may determine a maximum number of activations to a target row within a time period based on, for example, the architecture of the DRAM and a rate at which activations of a target row may corrupt data stored in adjacent rows of the DRAM. Once the number of activations in the time period is reached, adjacent rows should be refreshed to avoid corruption of the data stored in the adjacent rows.
The maximum number of activations to a target row within a time period may be conventionally referred to as the maximum activation count (MAC). The MAC is the maximum number of activations to a target row within a time period, namely the maximum activation window (tMAW), before the adjacent rows should be refreshed to avoid data corruption.
A situation associated with the corruption of data stored in an adjacent row due to frequent activations of a target row may occur when one or two “aggressor” rows target one “victim” row. For example, multiple target aggressor rows, between which the adjacent victim row is disposed, may be frequently activated. Therefore, the sum of the activations from the two aggressor rows for a given victim row should not exceed the MAC, as the activations to both the aggressor rows may contribute to the corruption of the data stored at the adjacent victim row.
If the MAC limit is reached within the maximum activation window, prior to sending another activate to a target row, the memory controller may either refresh all rows in the DRAM, perform a Targeted Row Refresh (TRR), to refresh only the rows adjacent to the over-activated target row, or throttle the activations to the target row such that the MAC limit will never be reached, which avoids having to perform the complete refresh of all rows or the TRR, but which delays fulfillment of the row activation.
In the above scenario, managing the MAC for the victim row is complicated by the fact that a memory controller, which controls activations to the rows in the DRAM, does not know the physical orientation of the rows. As such, the memory controller cannot track the activations to both of the aggressor rows with respect to a given victim row. To protect against exceeding the MAC for a victim row, an effective MAC value may be set to MAC/2 activations in the maximum activation window.
Managing the MAC limit conventionally requires tracking the number of activations that have been sent to each row of the DRAM within the maximum activation window. To truly track the number of activations to each row requires a counter for each row for each bank, and for each rank in the DRAM. In a DRAM with up to 4 ranks and 16 banks per rank, and 128K rows per bank, the number of counters would be 4×16×128K=8192K counters, with each counter requiring N bits. This quantity of counters and the associated space required for their management quickly become unmanageable from a power/area perspective of memory controller design.